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<a name="Options_002di960"></a>
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<p>
Next: <a href="Floating-Point_002di960.html#Floating-Point_002di960" accesskey="n" rel="next">Floating Point-i960</a>, Up: <a href="i960_002dDependent.html#i960_002dDependent" accesskey="u" rel="up">i960-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
</div>
<hr>

<a name="i960-Command_002dline-Options"></a>
<h4 class="subsection">9.17.1 i960 Command-line Options</h4>

<a name="index-i960-options"></a>
<a name="index-options_002c-i960"></a>
<dl compact="compact">
<dd>
<a name="index-i960-architecture-options"></a>
<a name="index-architecture-options_002c-i960"></a>
<a name="index-_002dA-options_002c-i960"></a>
</dd>
<dt><code>-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC</code></dt>
<dd><p>Select the 80960 architecture.  Instructions or features not supported
by the selected architecture cause fatal errors.
</p>
<p>&lsquo;<samp>-ACA</samp>&rsquo; is equivalent to &lsquo;<samp>-ACA_A</samp>&rsquo;; &lsquo;<samp>-AKC</samp>&rsquo; is equivalent to
&lsquo;<samp>-AMC</samp>&rsquo;.  Synonyms are provided for compatibility with other tools.
</p>
<p>If you do not specify any of these options, <code>as</code> generates code
for any instruction or feature that is supported by <em>some</em> version of the
960 (even if this means mixing architectures!).  In principle,
<code>as</code> attempts to deduce the minimal sufficient processor type if
none is specified; depending on the object code format, the processor type may
be recorded in the object file.  If it is critical that the <code>as</code>
output match a specific architecture, specify that architecture explicitly.
</p>
<a name="index-_002db-option_002c-i960"></a>
<a name="index-branch-recording_002c-i960"></a>
<a name="index-i960-branch-recording"></a>
</dd>
<dt><code>-b</code></dt>
<dd><p>Add code to collect information about conditional branches taken, for
later optimization using branch prediction bits.  (The conditional branch
instructions have branch prediction bits in the CA, CB, and CC
architectures.)  If <var>BR</var> represents a conditional branch instruction,
the following represents the code generated by the assembler when
&lsquo;<samp>-b</samp>&rsquo; is specified:
</p>
<div class="smallexample">
<pre class="smallexample">        call    <var>increment routine</var>
        .word   0       # pre-counter
Label:  <var>BR</var>
        call    <var>increment routine</var>
        .word   0       # post-counter
</pre></div>

<p>The counter following a branch records the number of times that branch
was <em>not</em> taken; the difference between the two counters is the
number of times the branch <em>was</em> taken.
</p>
<a name="index-gbr960_002c-i960-postprocessor"></a>
<a name="index-branch-statistics-table_002c-i960"></a>
<p>A table of every such <code>Label</code> is also generated, so that the
external postprocessor <code>gbr960</code> (supplied by Intel) can locate all
the counters.  This table is always labeled &lsquo;<samp>__BRANCH_TABLE__</samp>&rsquo;;
this is a local symbol to permit collecting statistics for many separate
object files.  The table is word aligned, and begins with a two-word
header.  The first word, initialized to 0, is used in maintaining linked
lists of branch tables.  The second word is a count of the number of
entries in the table, which follow immediately: each is a word, pointing
to one of the labels illustrated above.
</p>

<p>The first word of the header is used to locate multiple branch tables,
since each object file may contain one. Normally the links are
maintained with a call to an initialization routine, placed at the
beginning of each function in the file.  The <small>GNU</small> C compiler
generates these calls automatically when you give it a &lsquo;<samp>-b</samp>&rsquo; option.
For further details, see the documentation of &lsquo;<samp>gbr960</samp>&rsquo;.
</p>
<a name="index-_002dno_002drelax-option_002c-i960"></a>
</dd>
<dt><code>-no-relax</code></dt>
<dd><p>Normally, Compare-and-Branch instructions with targets that require
displacements greater than 13 bits (or that have external targets) are
replaced with the corresponding compare (or &lsquo;<samp>chkbit</samp>&rsquo;) and branch
instructions.  You can use the &lsquo;<samp>-no-relax</samp>&rsquo; option to specify that
<code>as</code> should generate errors instead, if the target displacement
is larger than 13 bits.
</p>
<p>This option does not affect the Compare-and-Jump instructions; the code
emitted for them is <em>always</em> adjusted when necessary (depending on
displacement size), regardless of whether you use &lsquo;<samp>-no-relax</samp>&rsquo;.
</p></dd>
</dl>

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